Section 8.7 of the 2017 LRM contains the text:
SystemVerilog does not require the complex memory allocation and deallocation of C++. Construction of an object is straightforward; and garbage collection, as in Java, is implicit and automatic. There can be no memory leaks or other subtle behaviors, which are so often the bane of C++ programmers.
I’ve always considered this passage more suitable for a book than an Official IEEE Standards Document.