Member variable to be only inherited by immediate child

SystemVerilog
,
3

In reply to bdreku:
I need to ensure ONLY IMMEDIATE child is able to access i.e. grand child should not able to access string s. With private/protected I am not able to achieve the same as shown below:


// Case 1: private qualifier
virtual class parent;
  private string s;
  // ..
endclass
 
class child extends parent;
  // s is NOT accessible here
endclass
 
class grand-child extends child;
  // s is NOT accessible here
endclass

// Case 2: protected qualifier
virtual class parent;
  protected string s;
  // ..
endclass
 
class child extends parent;
  // s is accessible here
endclass
 
class grand-child extends child;
  // s is accessible here
endclass

Am I missing something?