Logic - is a bit or integer?

SystemVerilog
1

Hi,

is it legal code from logic perspective ?

for example,

logic a=1;

a = a << 1;
a = a << 1;

// a=4 ?

Wanted to get a=4

2

In reply to alexd555:

  • logic is a scalar 4-state binary digit with the possible values 1’b0, 1’b1, 1’bx, or 1’bz
  • bit is a scalar 2-state binary digit with the possible values 1’b0 or 1’b1
  • integer is a signed integral vector made from a packed array of 32 logic digits.

You need a packed array of at least 3 digits to hold the decimal value 4.

3

In reply to dave_59:

Hi,

How can I do it dynamically ? assign array of logic ?
My goal is to sample coverage of series of bits.

I want to sample the changes of bit from 0 to 1 or 1 to 0

For example:

  covergroup do_update_check_cg;
 
    do_check_cp : coverpoint do_check {
      bins do_0_0_1  = {3'b001};
      bins do_1_0_0  = {3'b100};   
      bins do_1_0_0  = {3'b101};   
    }
  endgroup : do_check_cg
4

In reply to alexd555:

I do not follow your line of questioning. I give up.