Logic - is a bit or integer?

SystemVerilog
3

In reply to dave_59:

Hi,

How can I do it dynamically ? assign array of logic ?
My goal is to sample coverage of series of bits.

I want to sample the changes of bit from 0 to 1 or 1 to 0

For example:

  covergroup do_update_check_cg;
 
    do_check_cp : coverpoint do_check {
      bins do_0_0_1  = {3'b001};
      bins do_1_0_0  = {3'b100};   
      bins do_1_0_0  = {3'b101};   
    }
  endgroup : do_check_cg