Logic for 'x' value

SystemVerilog
,
1

I have created one logic to monitor whether a signal is 0/1.

task xyz();

if(abc == 1)
begin
task123;
end
else
begin
task234;
end

the value of abc variable is taken on next clock cycle, but for current clock cycle it is treated as ‘X’.

problem here in above task is that, initially the value of abc variable is neither 0 nor 1. hence it is ‘X’, so it is treated as ZERO, and he task234 is executed.

Moreover, i want my abc varaible value to be “logic 1” for first transaction and then randomizing it for the rest.

2

In reply to hvgbl:

How you are calling this task “xyz”?

3

In reply to Naven8:

I am defining this task “xyz” as a virtual task.

task start();
fork
forever
begin
xyz();
end
join

endtask

4

In reply to hvgbl:

Still no where near enough code shown about where abc is declared and how its value is set to be able to understand your question. If you want to be 1, then either initialize it to 1 in its declaration, or set it to 1 when you want it to be.

5

In reply to dave_59:

for first time use of this abc variable, i want its value to be logic 1.
and for rest of its use, i want it to be randomize…!

6 
class A;
rand logic abc = 1;
task runme;
$display(abc); // first reference to abc is displays 1
forever begin
        randomize();
        $display(abc); // rest of time, abc is randomized
        end
endtask

I am sure this does not answer your question, but you have not given us any clue about what defines a “use” of abc.

7

In reply to hvgbl:

You can swap your code to check for “abc == 0” so by default when data is X it will choose else path.