Logic for 'x' value

SystemVerilog
,
6 
class A;
rand logic abc = 1;
task runme;
$display(abc); // first reference to abc is displays 1
forever begin
        randomize();
        $display(abc); // rest of time, abc is randomized
        end
endtask

I am sure this does not answer your question, but you have not given us any clue about what defines a “use” of abc.