In reply to ben@SystemVerilog.us:
Thanks Ben for that clarity.
I also have tried using the below syntax for the $display of latency values.
Basically,
(expression, $display(…))
property p_min_time();
realtime start_time;
@(posedge sig1) (1,start_time = $realtime) |->
@(posedge sig2) (($realtime - start_time) == duration,$display("\t Latency_checker= %d ",$realtime - start_time));
endproperty
assert property (p_min_time)
else `uvm_error (“p_min_time,$sformat(”%m FAIL p_min_time"));
How does the $display display the latency values when there is a failure, I am only seeing values in log during the passing of assertion. In the failure case it did not show in log what value was the latency.