Latency between 2 signals

SystemVerilog
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6

In reply to verif4ravi:
Assertions don’t rely on clocks, but on lead cloking events.
Also an assertion needs ONE leading clocking event to start the attempt.
Example:

event e1; 
bit clk. a, b, c, d;
// lead clock  
assert property(@(posedge clk) a |-> @(negedge b) d  ...); // multiclock
assert property(@( clk) a |-> ...); // every transition of clk 
assert property(@(c) a |-> ...);
assert property(@(e1) a |-> ...);