In reply to ben@SystemVerilog.us:
Hi Ben,
After some more analysis found that the latency between sig2-sig1 was appearing in real value (115.563ns) and not an Integer Value (may be that’s the reason it was causing a failure for another few cycles), so have accordingly changed the checks to a range.
property p_min_time();
realtime start_time;
@(posedge sig1) (1,start_time = $realtime) |->
@(posedge sig2) (($realtime - start_time) >= 115ns) && (($realtime - start_time) <= 116ns);
endproperty
The above, then works fine for my requirement.
Let know if real value delays have to be handled in a different way.
Another query that I have is how do we know what clock the above assertion is working on? Is it directly understood that the clocks on which sig1 and sig2 are synchronous to, is the clock in which the assertion is getting triggered.