Large memory footprint assertion

SystemVerilog
1

Hi,

I have a assertion some thing like below:
property READY;
@(posedge CLK)
(VALID & !READY )|-> ##[1:$] (!VALID | READY));
endproperty
ready: assert property (READY);
When i use above assertion it was giving the below warning:

Warning-[SVA-OPTCOV-LMFA] Large memory footprint assertion
The assertion ‘ready’ has the potential to consume a large amount of memory.
Please examine the assertion for the use of large or unbounded delays and repetitions.

How to get rid of this warning?

Thanks,
Rajasekhar

2

In reply to sekhar129:

  • Without a $rose you create at every clock edge a successful attempt and thus a new thread.
  • Use logical operators when dealing with Booleans.
  • Assertion looks OK.
 
$rose(VALID && !READY )|-> 
            strong(##[1:$] (!VALID || READY)));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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