Issue with assertion

SystemVerilog
,
1 
assert_region   :   assert property(@(posedge clk)
disable iff(ahb_htrans==2'b0 )
(!mpu_region_vr) |-> ((ahb_hnonsec ==  mpu_en_s_r) && (ahb_htrans != 2'b0))  ) $fatal("\nERROR:Wrong value of ahb_hnonsec for valid AHB transfer ");

the above assertion not getting triggred properly and giving me false failure I am not sure weather I can use $Fatal directly or I have to use in else part only…but I can not change my condition as well so whenever above gets satisfied I need to set a fatal

what would be wrong with above code ?

regards
abhi

2

In reply to abhijain:
There are 2 ways that a property can be true:

  1. true nonvacuously
  2. true vacuouly
    If a property is true then the PASS action block is fired.
    If a property is false then the FAIL action block is fired.

Some tools set, as default, the PASS action block to fire ONLY ON NONVACUOUS PASSES.
Others display the PASS action block on any pass, vacuous or NONVACUOUS.
This maybe is what you see happening, the pass action block on NONVACUOUS passes.
Ben Ben@systemverilog.us

3

In reply to ben@SystemVerilog.us:
In any case, you should be writing your assertion so that the $fatal gets called when an assertion fails. Doing it the other way will have your action block issuing a fatal message when it passes, and an error message when it fails.

4

In reply to dave_59:

You’re correct Dave, an assertion defines the expected good condition and alerts of an error. . Thus, it is rare to write action blocks on passes, unless for debug or very rare conditions to set a flag
.
Ben

5

In reply to ben@SystemVerilog.us:
If your option is to have some action after a property is true you should be using thecover property instead of assert property. The syntax for the cover property is:

cover_property_statement::=
  cover property ( property_spec ) statement_or_null

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us