Issue with assertion

SystemVerilog
,
2

In reply to abhijain:
There are 2 ways that a property can be true:

  1. true nonvacuously
  2. true vacuouly
    If a property is true then the PASS action block is fired.
    If a property is false then the FAIL action block is fired.

Some tools set, as default, the PASS action block to fire ONLY ON NONVACUOUS PASSES.
Others display the PASS action block on any pass, vacuous or NONVACUOUS.
This maybe is what you see happening, the pass action block on NONVACUOUS passes.
Ben Ben@systemverilog.us