Is using interfaces for SVAs instead of a simple bind file a good idea?

SystemVerilog
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1

Hi,

I had always used a bind file to bind my SVAs to the RTL Design modules in my verification environment. However is it a good idea to use interfaces to connect Assertions to the RTL module? I personally find interfaces to be more complex to handle as compared to a simple bind file. Any thoughts/feedback (Pros and cons) on this is highly appreciated.

2

In reply to pare_9:
SVA in interfaces is for the verification of the RTL as a black box.
A SV checker or module bound to the RTL provides more flexibility since it has access to the internals of the RTL, and thus can do both, white and black box verification.

Uvm requires interfaces for connections, and if you want to add assertions using class variables, you can copy the values of the classes into the interfaces and do assertions there. See my paper at
SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment