In reply to jms8:
SystemVerilog does not have pointers to memory; it only has handles to dynamically allocated class objects. A class handle is an safe/opaque pointer with very limited operations that can be performed on it. What you can do is to wrap each variable in a class, and construct objects of that class whose handle can be passed around.
There may be other solutions, but I would need more details on the actual environment you are working with.