Is there a way to pack the SystemVerilog structures using the packing macros?

UVM
1

Hi,

I have a packed structure as a rand variable in my sequence item. Is there a way to pack and unpack the entire structure (or structure of structures) using the uvm packing / unpacking macros, without addressing the individual elements?

Thanks,
Madhu

2

In reply to mseyunni:

Not sure which macros you are referring to.

3

In reply to dave_59:

uvm_packing macros such as uvm_field_in, uvm_field_obj etc

4

In reply to mseyunni:

Those are known as the field automation macros and the only handle a limited of data types.

Use SystemVerilog’s bit-streaming cast and the streaming operator to pack/unpack your class members.