Is System Level Testcase different from a block level testcase? And what is a test vector?

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I usually see these terms, system level testcase, block level testcase. Are they different?
Because in my understanding, if you can create block level testcase then you can also create system level testcase.
I’m not sure which is harder or maybe both testcases have the same difficulty of creating?

I also heard the term, test vector. What is this?

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In reply to Reuben:

A block-level testcase belongs to a block-level testbench and a sytem level testcase belongs to a system level testbench. The testcase is doing always the same. It is configuring the corresponding testbench an d executinf a sequence/virtual sequence to execute sequence items.
Testvector is used other types of tests like scan test.

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In reply to Reuben:
In a block level testcase, you need to provide stimulus and response components for blocks that are not part of the simulation. In a System-Level testbench, those components become passive because now you have all the blocks in place. But you still have prove stimulus for the parts of the system that are not being simulated, or whatever is external to the “System” But the monitors and scoreboards you used at the block level can be reused at the system level.

A test vector is older terminology from applying stimulus once cycle at time with all the inputs to the DUT being concatenated into a single “vector”. Typically used in manufacturing tests, not functional verification.

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In reply to dave_59:

In reply to Reuben:
In a block level testcase, you need to provide stimulus and response components for blocks that are not part of the simulation. In a System-Level testbench, those components become passive because now you have all the blocks in place. But you still have prove stimulus for the parts of the system that are not being simulated, or whatever is external to the “System” But the monitors and scoreboards you used at the block level can be reused at the system level.
A test vector is older terminology from applying stimulus once cycle at time with all the inputs to the DUT being concatenated into a single “vector”. Typically used in manufacturing tests, not functional verification.

Hi dave,

Thanks for the reply. I also heard some engineers say if your testcase is used in silicon. What is this?

Then there are also testcases that are created from C-language. They use this if the DUT is a microcontroller. What is this? What’s the purpose of using C-Language? Is this what they call a software testing? What is it for?

Regards,
Reuben

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In reply to Reuben:

In reply to dave_59:
I also heard some engineers say if your testcase is used in silicon. What is this?

That is what I meant by used in manufacturing - when your test is applied to a supposedly working piece of silicon. That is a test to make sure the manufactured part matches the specification used to build it.

The rest of your question is a very broad topic. You can use many different languages to create stimulus to a DUT. It really depends on what the application is and the resources available to write the code.

Software testing generally refers to testing software that is part of a product deliverable, not software used to test hardware.

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In reply to dave_59:

I see. Thanks dave!

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In reply to dave_59:

What about modeling the analog circuits? Is this a part of system level?
Does system level means that the testbench should be at the chip’s pin level?