Is System Level Testcase different from a block level testcase? And what is a test vector?

In reply to Reuben:
In a block level testcase, you need to provide stimulus and response components for blocks that are not part of the simulation. In a System-Level testbench, those components become passive because now you have all the blocks in place. But you still have prove stimulus for the parts of the system that are not being simulated, or whatever is external to the “System” But the monitors and scoreboards you used at the block level can be reused at the system level.

A test vector is older terminology from applying stimulus once cycle at time with all the inputs to the DUT being concatenated into a single “vector”. Typically used in manufacturing tests, not functional verification.