Is it possible to verify, if the signal rose within a cycle in SVA?

SystemVerilog
,
7

In reply to Adarsh24:
Actually, you do not need any assertion here.
Signal ‘a’ is an output of flop with a hold delay.
Signal ‘b’ is a delayed combo out of ‘a’.
Thus, what you have is basically a wire with internal delays.
The concern is a setup and hold, and this is best done by using the system functions.


module setup_time_check(input clk, data); //  SystemVerilog.us/vf/hold.sv
    timeunit 1ns;  timeprecision 100ps;
    let tSU=2ns; 
    let tHLD=2ns;
    bit notifier1;
    specify
        $setuphold( posedge clk, data, tSU, tHLD, notifier1 );
    endspecify 
endmodule

module top2(output logic clk, d);
 realtime duration= 2.0ns;
   …
setup_time_check setup_time_check1(clk, d); // built in 1800 setup and hold 
// *** If you insist on using assertions, then assert those properties 
property hold_chk;
    realtime clock_sample;
    @(posedge clk) (1,clock_sample = $realtime) |-> 
       @(d) ($realtime - clock_sample) >= duration;
 endproperty : hold_chk

property setup_chk;
   realtime clock_sample;
   @(d) (1,clock_sample = $realtime) |-> 
   @(posedge clk) ($realtime - clock_sample) >= duration);
endproperty : setup_chk

If you insist on using an assertion for your ‘a’ ‘b’ concern, then you can simply write


// +--+                                 +--+
// |FF|----a----(gate_delays)------b--->|FF|---c
// +--+                                 +--+
// at every clocking event the sampled value of 'a' == sampled value of 'b'
ap_ab: assert property(@ (posedge clk) a==b);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

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