In reply to ben@SystemVerilog.us:
Hi,
Sorry I couldn’t get a chance to try it out yet.
I don’t think Maddy’s check is what I initially wanted.
I want to make sure b goes high before the next clock edge. Not at the clock edge.
Ideally I want to check if b goes high immediately as a goes high.
Yes, a is a flop out and b is a delayed combo out of a.
This is not an actual problem I observed. Something that I was thinking about.
Im thinking this won’t be an issue since there will be clk-to-q delay and a will be checked at next edge anyway. By that time b will be high.
So by this logic I think Maddy’s suggestion will work.