In reply to maddy0812:
“async signal ‘b’ that should go high immediately as trigger ‘a’ goes high ideally”
Looks like ‘b’ is a buffered (delayed) version of ‘a’ which is the output of a flop.
The following @(posedge clk) a |-> ##[0:1] b;
does not “check for b to go high starting from 0 all the way to 1 clock cycle.
assuming your delay isnt greater than 1 clock cycle.”
It is not a continuous check. All it says is that in the Preponed Region, the sampled values of ‘a’ and ‘b’ have the same values in the current and next cycle.
‘b’ can glitch at any time between those sampled times.
The assertion is OK, if that is what you want.