Is it possible to map 2 different sequencers to a reg_map one for read one for write?

In reply to chr_sue:

AXI does not allow concurrent RD and WR accesses

I believe this is incorrect ( Feel free to correct me ) .
The AXI Specification doesn’t restrict such concurrent accesses .

I discussed this with a few friends ( one of them used to work in VIP team for AXI ) and both of them agreed with concurrent write and read access being legal .

After all they are called independent channels in the specification .

The following is from AXI 3 Specification .


9.1 About the data buses 

The AXI protocol has two independent data buses, one for read data and one for write data.
Because these data buses have their own individual handshake signals, it is possible for data
transfers to occur on both buses at the same time.