Is it legal to assign struct of a particular type to that of a different type in verilog?

SystemVerilog
,
1

I am seeing code like below in RTL and the build tool does not throw any warnings or errors about it.
Is it legal to do assign a = b as shown below?



typedef struct packed {
    logic [3:0] a1;
    logic [7:0] a1;
} A_t;

typedef struct packed {
    logic b1;
    logic [5:0] b2;
} B_t;

module rdv_chip (input gclk, input reset_l, input reset);

    A_t a;
    B_t b;

    assign a = b; // <<<<<<<<<<<<<< Any way to throw a warning or error here?

endmodule
2

In reply to va_pal:

Due to its C heritage SystemVerilog is not a strongly-typed language, like Ada / VHDL. Your specific case is legal and is specified in the LRM as

When the right-hand side evaluates to fewer bits than the left-hand side, the right-hand side value is
padded to the size of the left-hand side. If the right-hand side is unsigned, it is padded according to
the rules specified in 11.6.1. If the right-hand side is signed, it is sign-extended.

however the LRM also goes on to say

Implementations can, but are not required to, warn or report any errors related to assignment size mismatch
or truncation. Size casting can be used to indicate explicit intent to change the size (see 6.24.1).

There are probably linting tools that can flag this use.

3

In reply to sbellock:

More specifically, SystemVerilog is not strongly typed when it comes to packed types. I only see tool warnings when connecting mismatched port sizes.

If you want stringer types, use an unpacked struct instead. Then you will need to use expect casts if you need to use the variable in as an integral type.

4

To Dave: 11.6.1 only talks about determining bit lengths and doesn’t actually specify what the padding should be if the right-hand side is unsigned. It should be 0’s obviously.