In reply to va_pal:
Due to its C heritage SystemVerilog is not a strongly-typed language, like Ada / VHDL. Your specific case is legal and is specified in the LRM as
When the right-hand side evaluates to fewer bits than the left-hand side, the right-hand side value is
padded to the size of the left-hand side. If the right-hand side is unsigned, it is padded according to
the rules specified in 11.6.1. If the right-hand side is signed, it is sign-extended.
however the LRM also goes on to say
Implementations can, but are not required to, warn or report any errors related to assignment size mismatch
or truncation. Size casting can be used to indicate explicit intent to change the size (see 6.24.1).
There are probably linting tools that can flag this use.