Is it by any chance possible to access a net(internal in DUT) through UVM environment?

UVM
,
1

I have scenario where I need to tap the value at a net that is internal to the DUT.
I have to do so because, after the net is connected to another block within DUT, the output is frequency domain and I have to do some comparisons before that happens.

I am not sure if I was able to put this question correctly, but any ideas or a work around will be helpful.

2

See the probe example from my DVCon paper:

https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection

3

In reply to dave_59:

Dear Dave,
According to the concept of Black , White and Grey box verification,
Black box:- We don`t have any access to the internal signal of DUT.
White Box :- We can access any intenal signal of DUT.
Grey box :- We have a limited access to the internal signal of a DUT.

So, in this case instead of black box, @Shweta has to use white box or probably Grey box verification approach.Or is there some other way.? If it is so.
1.Will our testbench be remain that reusable.?
2.Exactly how we can switch from one approach to another? Are there some special constructs in library which helps us to do so ?

Regards
Ujjwal

4

In reply to Ujjwal Kaushik:

Thanks Dave, Ujjwal,
That is something worth exploring. Also, can I declare an internal net as coverage point.?