Interview Questions on Assertions

SystemVerilog
,
4

In reply to Subbi Reddy:

Below are my assertions for these. I made use of the gotooperator [->n], a very useful operator. I wrote several responses on this. Do a google search on
verificationacademy cohen “goto” first_match

Would be nice to see how you wrote the ones you wrote.



module top; 
    timeunit 1ns/100ps;
    `include "uvm_macros.svh"
     import uvm_pkg::*;
     bit clk, a, b;  
     bit[15:0] DI, DO;
     bit[15:0] mem[31:0]; 
     typedef enum {ACTIVE1, START} st_t; 
     st_t state;      
     initial forever #10 clk=!clk;  

   // 1) a and b are environment signals, which can be given at any time, but should never be given together
     ap1_not_a_and_b: assert property(@ (posedge clk) not(a && b) );  
      
   // 3) if there is a sig a, followed by 3 consective sig  b, 
   // then in each of the 3 cycles the data written(DO) is equal to the data mem(DI).
   //  $past( expression1 [, number_of_ticks] [, expression2] [, clocking_event]) 
     ap3_a3bmem: assert property(@ (posedge clk) a ##1 b[*3]  |-> 
        DO==mem[DI] && $past(DO, 1)== $past(mem[DI],1) && $past(DO, 2)== $past(mem[DI],2)); 

   // 5) If there are two occurences of sig a rising with state=ACTIVE1, 
   // and no sig b occurs between them, then within 3 cycyles of the second rise of sig a, START must occur.
     ap5_aa_nob: assert property(@ (posedge clk) 
           $rose(a) && state==ACTIVE1 ##1 $rose(a) && state==ACTIVE1[->1] intersect !b[*1:$] |-> 
            ##[1:3] state==START );  
    
    // 6. show a sequence with 3 transactions (in which sig_a is asserted 3 times).
     sequence q_a3; 
        @ (posedge clk)  a[->3];   
     endsequence        
    
       initial begin 
         repeat(400) begin 
             @(posedge clk);   
             if (!randomize(a, b, state, DI, DO)  with 
             { a dist {1'b1:=1, 1'b0:=1};
               b dist {1'b1:=1, 1'b0:=2};  
               DO dist {16'b0000:=1, 16'H000F:=1};  
               DI dist {16'H0000:=1, 16'H000F:=1}; 
         }) `uvm_error("MYERR", "This is a randomize error");
         end 
         $finish; 
        end  
 endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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