Interface Class and Abstract Class and when to use which one?

SystemVerilog
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Hello -

I am unable to understand why there are two similar functionality feature available in SV? Interface Class and Abstract Class and what is best usecase? Generally I prefer abstract class where I want env to follow certain implementation but then question arise, why not interface class? I am kind of unclear about each of these. Your input, would help.

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In reply to NPat:

Yes, there is some small overlap in the use cases between the two features, but the key motivation for interface classes is multiple inheritance.

See these DVCon 2016 papers for examples(attached)

And these blogs

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In reply to dave_59:

Thank you Dave for your response and also pointing out couple of links. It seems interesting. I will go through them in details. Thanks again…!!