Instruction sequence generator for verifying a processor

SystemVerilog
1

Dear friends,
I need some help in constrainsts.
I created a base class inst_class with all properties defined by the instruction architecture and a method to form the instruction based on opcode type selected (eg. arith, control etc).
I created a scenario class which has a dynamic array of the inst_class named items.
the base scenario class is extended by common instruction scenario class which has constraints to create valid sequences.

the common instruction scenario class is extended by dep_scenario which has more constraints to force instruction with dependency.
the common instruction scenario class is extended by arith_scenario which has more constraints to generate only arithmetic instruction.

In the ENV class i have a queue(named scenario_c) of type common instruction scenario.

Now the generation happens like this.
Program block creates few objects of type arith_scenario, dep_scenario and common_scenario and pushes down the queue.

In the ENV class i have run task which goes like this:

2

In the ENV class i have run task which goes like this:

foreach scenario_c[i]
for (j=0;j < scenario_c.length < j++)
begin
scenario_c[i].items[j]=new;
scenario_c[i].items[j].randomize();
scenario_c[i].items[j].form_instr();
end

Now the problem is the constriaints of arith_scenario, dep_scenario and common_scenario are not passed to inst_class.

How can i do that.
Plz help

3

In reply to war_isbest:

How about:

foreach scenario_c[i]
  begin
  for (j=0;j < scenario_c.length < j++)
     scenario_c[i].items[j]=new;
  scenario_c[i].randomize();

And have the form_instr() method called as part of post_randomize()

4

In reply to dave_59:

///scenario.sv///////
`include "../tb/verilog/inst_class.sv"
class instruction_scenario extends inst_class;
rand int unsigned scenario_kind;
rand int unsigned length=50;
rand inst_class items[]; 
rand int unsigned repeated;


function int unsigned define_scenario (string name,
                                       int unsigned max_len);
$info("secenario is %s",name);
this.length=max_len;                                       
endfunction
 
endclass

///////dep_scenario.sv//////////
`include "../tb/verilog/common_scenario.sv"
class dep_scenario extends common_instruction_scenario;
  
int SCN_MORE_DEP;
int base_addr, addr_range;
constraint more_dep_scn_valid {
  //check below line 15/10/12
   if (scenario_kind == SCN_MORE_DEP) {
     
      repeated == 0;         length == 10;
      foreach (items[i]) {
         items[i].rd inside {[base_addr : base_addr+addr_range]};
         items[i].rs1 inside {[base_addr : base_addr+addr_range]};
         items[i].rs2 inside {[base_addr : base_addr+addr_range]};
      }
   }
}

//constraint depcheck 
//{
// items[23].kind ==BA ;
//}


function new;
  super.new();
    this.base_addr = 0;
   this.addr_range = 4;
  
   this.SCN_MORE_DEP = define_scenario ("SCN_MORE_DEP", 40);
endfunction


function void pre_randomize ();
   super.pre_randomize();
   this.base_addr = 0;
   this.addr_range = 4;
endfunction


endclass

class arith_only_scn extends common_instruction_scenario;
   int SCN_ARITH_ONLY;
   constraint arith_only_scn_valid {
      if (scenario_kind == SCN_ARITH_ONLY) {
         repeated == 0;
         length inside {[5:10]};
         foreach (items[i]) {
            foreach (items[i]) {
               items[i].opcode_type == ALU;
            }
         }
      }
   }
   function new ();
      super.new();
      this.SCN_ARITH_ONLY = define_scenario ("SCN_ARITH_ONLY", 30);
   endfunction
endclass

//////////////////////////////////

So what i understand is instead of randomizing the instruction objects i shall randomize the arith_only_scn and dep_scenario classes.Will these constraints written in the form of items[i].any_property=any_value will be passed to the objects pointed by the handles stored in the dynamic array of instructions?

5

In reply to war_isbest:

Yes. Whenever you randomize a class, when that top-level class contains other child classes and their handles are declared with rand, the constraints in the top-level and all the children are considered together as a single set of constraints. (by top-level, I just mean the class object that randomize was called on).

6

In reply to dave_59:

Which of the below method is correct for writing a constraint if i want CALL-> ALU sequence?

foreach(items[i])
{
if(i%2 ){
         items[i].opcode_type=CALL;
         items[i+1].opcode_type=ALU;
         }

}

OR

foreach(items[i])
{
if(i%2 ){
         items[i].opcode_type=CALL;
         foreach(items[j] && j=i+1)         
         {
          items[j].opcode_type=ALU;
         } 
        }

}
7

In reply to war_isbest:

plz comment on the above.
if I use the second method , it seems to slow down the simulator(questasim 10.0)