Instruction sequence generator for verifying a processor

SystemVerilog
3

In reply to war_isbest:

How about:

foreach scenario_c[i]
  begin
  for (j=0;j < scenario_c.length < j++)
     scenario_c[i].items[j]=new;
  scenario_c[i].randomize();

And have the form_instr() method called as part of post_randomize()