Instantiate a VHDL block to SV

SystemVerilog
1

Hi I’m trying to make a verification using SV and UVM…

I have some blocks write in VHLD, I need to map those VHDL blocks but i have some problems with the blocks that has Generic declaration:

ENTITY SMCS332_top IS
   GENERIC( 
      DEVICEID : string;
      SMCSID   : integer
   );
   PORT( 
      clk_i      : IN     std_logic;
      clk_pll_i  : IN     std_logic;
      hadr_i     : IN     std_logic_vector (7 DOWNTO 0);
      hrd_ni     : IN     std_logic;
      hsel_ni    : IN     std_logic;
      hwr_ni     : IN     std_logic;

                .
                .
                .
                .
                .

I can map the ports but i dont know how I need to do with the Generic…
I try:

SMCS332_top SW_A (
     //Port declaration
     );
defparam SW_A.DEVICEID = "name"; (its a string)
defparam SW_A.SMCSID = 0; (its an integer)

but Questasim when i try to simulate says:
** Error: (vsim-10000) VME_UVM_Top.sv(335): Unresolved defparam reference to ‘SW_A’ in SW_A.DEVICEID.

Region: /VME_UVM_Top

** Error: (vsim-10000) VME_UVM_Top.sv(336): Unresolved defparam reference to ‘SW_A’ in SW_A.SMCSID.

Region: /VME_UVM_Top

then if i didnt give a value questasim says:

** Fatal: (vsim-3350) Generic ‘DEVICEID’ has not been given a value.

Anyone knows how I can fix this error??

Thanks in advance!!!

2

You cannot use a defparam across the language boundary. Please use in-line parameter overrides instead of defparam.

SMCS332_top 
     #(
       .DEVICEID("name"), 
       .SMCSID(0)
      )
      SW_A (
     //Port declaration
     );

You should remove the use of defparam regardless.

3

In reply to dave_59:

Hello Dave,
I want the assigned generic value not to be hard-coded. I want it to be able to configure it with each uvm test.
(I instantiate the VHDL dut in the top module of the verification environment as usual).

Thanks

4

In reply to Mustafa:

That is not possible using generics. Generic values must be fixed at elaboration.

Two methodologies I see frequently are:

  1. Each test has an associated package that supplies the constant values used to configure the DUT. You may have many tests for one package or many packages for one test as well. Your scripts need to match up the test to the proper package.

  2. When you want to randomize the configuration, you need a two-step flow to a) create the randomized package and b) compile and run the DUT with the randomized package.

5

In reply to dave_59:

But you can change the value of the generic DURING instantiation on the vsim line:

alias elab_debug1 {eval vsim -novopt -t ns -L work -L UTIL1164 -L textutil -G SMCSID=0 -G DEVICEID=“name” -l “my_logfile1.log” $TOP_LEVEL_NAME}

alias elab_debug2 {eval vsim -novopt -t ns -L work -L UTIL1164 -L textutil -G SMCSID=1 -G DEVICEID=“name2” -l “my_logfile1.log” $TOP_LEVEL_NAME}

etc.

And then you schedule different runs):

elab_debug1
run -all

elab_debug2
run -all