In reply to stas2005:
I opened a case to Synopsys, and this is the answer I got. Thought it might help to someone else.
You can see below (LRM) that Assignments to variables declared as input ports shall be illegal.
23.3.3.2 Port connection rules for variables If a port declaration has a variable data type, then its direction controls how it can be connected when instantiated, as follows:
— An input port can be connected to any expression of a compatible data type. A continuous assignment shall be implied when a variable is connected to an input port declaration. Assignments to variables declared as input ports shall be illegal. If left unconnected, the port shall have the default initial value corresponding to the data type.
When you have logic inside the port declaration of addr, addr become variable (not net). When you omit logic, addr become net and it legal to assign to it directly.
You can do two experiments to see that without logic, addr become wire (net).
module A (
input [31:0] addr ///<— omit logic
//input logic [31:0] addr
);
wire [31:0] addr; ///<---- No error! legal logic [31:0] addr; ///<— ERORR! Ilegal
wire [31:0] addr_local;
assign addr_local = addr;
endmodule