Input port cannot be driven

SystemVerilog
3

In reply to dave_59:

Thank you Dave,
I use latest version of VCS (L-2016.06-1). I tried with different versions, but still getting the same error:

Error-[VIPCBD] Variable input ports cannot be driven
tb.sv, 25
Variable input ports cannot be driven.
The input variable port “addr” of module “A” cannot be driven.
Source info: assign tb.a.addr = tb.io_if.addr;
Module ‘A’ is defined at “tb.sv”, 1

Unfortunately, I can’t use your suggestion in our TB without modifying a lot of files.
Maybe i’m missing some flags. I used the following command for this example:
vcs -lca -sverilog tb.sv

Thanks