Input port cannot be driven

SystemVerilog
2

In reply to stas2005:

The error that you are getting is not correct. Please check the version of the tool that you are using and contact your vendor. There is no difference between

module A (
  input logic [31:0] addr
);

and

module A (
  input [31:0] addr
);

because they both declare ports that are implicitly ‘wire’. The first has an explicit data type 'logic, and the second has an implicit data type ‘logic’. See section 23.2.2.3 Rules for determining port kind, data type, and direction in the 1800-2012 LRM.

However, you can change the way you instantiate your dut to:

module tb;
 
   A a(io_if.addr);
   dut_io io_if();
 
endmodule