Info regarding built in sequences for memory


I need clarification regarding the usage of built in sequences in RAL to verify memories in DUT.
For registers, write and read methods will write and read from DUT and compares against mirrored values in RAL(Mentioned in write and read APIs in verification academy).
Does memory built in sequences also does similar operations like for write and read it will write and read from DUT and compares against the values in memory in RAL ?

Request to help on this.


In reply to Prashanthp436:

You can use the ‘Register Access Test Sequences’ for testing your registers and checking the results. See the UVM Ref Manual for more details.

For registers the built in sequences will compare the read value from DUT against the mirrored value in RAL register if we call
But for memories, it has single value(no desired/mirrored values). when we call, it will read the data from DUT. but it is not comparing against the values in RAL memory. then how can we know that RAL memory is in sync with DUT memory ?
And do we have any exclusive methods to read only memory contents in RAL and not DUT ?(just like peek() does DUT read only)

In reply to Prashanthp436:

how can we know that RAL memory is in sync with DUT memory
The RAL memory is just meta info like length & width. It does NOT contain a copy of the data. Unlike registers, memories are not mirrored because of the potentially large data space

Hello chris.
So may i know what is the purpose of using memory in RAL other than memory configuration details ?
If we wanted to do some TB testcases that are dependent on memory contents, so backdoor access to DUT memory is the only way ?

In reply to Prashanthp436:

uvm_mem gives you a common API for all addressed mapped memories same as RAL. It also gives you other features common to RAL like iterators and lookup-by-name.

Back door is probably the easiest way to access contents. You could also manually mirror your memory.

In reply to dave_59:

Thanks Dave!

RAL also lets you write protocol-independent sequences such as:

rm.mem.write(status, offset, 42);, offset, data);
if (data != 42) 
  `uvm_error("BAD", "STUFF")