In reply to dave_59:
In reply to nex:
There’s no way within SystemVerilog to iterate over any set of characters embedded in an identifier name. Note that after synthesis flattens and optimizes, it is possible that not all the consecutive names exist. So you are left with doing this manually in a text editor, or some other script to generate the code.
Hi Dave, thank you for your answer
I was expecting this kind of limitation but hoped there was a (maybe tricky) way to bypass it.
Good point about the synthesis not preserving the path or instances, this is not the case with my code but it could happen in some case.
Best regards,
Nils