Increment operator - order of execution

SystemVerilog
,
1

Would the increment happen Left to right or right to left in the following case:

   desc.src_addr = {rdata[i++],rdata[i++],rdata[i++],rdata[i++],rdata[i++],rdata[i++],rdata[i++],rdata[i++]};

Assuming i = 0 at the start of the above statement, would the end resolution be which of the two below:

   desc.src_addr = {rdata[0],rdata[1],rdata[2],rdata[3],rdata[4],rdata[5],rdata[6],rdata[7]};

   desc.src_addr = {rdata[7],rdata[6],rdata[5],rdata[4],rdata[3],rdata[2],rdata[1],rdata[0]};

Is there anything in LRM that talks about this?

Obviously, my aim is to avoid hardcoding the indices in the above statement to avoid typo and oversight issues.

Thanks in advance.

2

In reply to verif_learner:

I tried a simple example. I think the increment happens in a single step as if all the post increment operators get the same value before the execution of the statement.

module abc;
  int index;
  bit [7:0] src;
  bit [7:0] dst;

  initial begin
    index = 0;
    src = 8'hAA;
    dst = {src[index++],src[index++],src[index++],src[index++],src[index++],src[index++],src[index++],src[index++]};

    $display ("src %h dst %h index %d",src,dst,index);
  end
endmodule

Output: src aa dst 00 index 1

It would be good to know what LRM says about this though.

3

In reply to verif_learner:

It would be good to know what LRM says about this though.

Yes, it would be good to know what the SystemVerilog LRM says when writing SystemVerilog code. Do you have a copy?

See section 11.4.2 Increment and decrement operators and look for the word undefined.

A much better way of writing this code would be using the streaming operator, section 11.4.14 Streaming operators (pack/unpack)