Increment operator - order of execution

SystemVerilog
,
2

In reply to verif_learner:

I tried a simple example. I think the increment happens in a single step as if all the post increment operators get the same value before the execution of the statement.

module abc;
  int index;
  bit [7:0] src;
  bit [7:0] dst;

  initial begin
    index = 0;
    src = 8'hAA;
    dst = {src[index++],src[index++],src[index++],src[index++],src[index++],src[index++],src[index++],src[index++]};

    $display ("src %h dst %h index %d",src,dst,index);
  end
endmodule

Output: src aa dst 00 index 1

It would be good to know what LRM says about this though.