In an SV package, does anyone know a slick way to `include multiple files without individually specifying them? For example, include all .sv files found in a folder? Everytime I add a new file for a package to include, I’ve got to go update the package file itself. a small annoyance
package sv_lib_pkg;
import uvm_pkg::;
`include “uvm_macros.svh”
import bcm_typedef_pkg::;
`include ALL // something like this
endpackage
In reply to bmorris:
There is nothing within SystemVerilog that allows you to do this.
There are a number of code generators that do this for you. But the simplest alternative would be to compile the package in multiple files without the use of `include by putting the package header is a separate file and all the other files on the compilation command line.
compile sv_lib_header.sv folder/*.sv sv_lib_footer.sv
where the header and footer files contain the package and endpackage keywords respectively.
In reply to dave_59:
cool technique. It works well. I wonder if the compiler will automatically figure out the correct compile order if any dependencies exist between the files. thanks.