In reply to bmorris:
There is nothing within SystemVerilog that allows you to do this.
There are a number of code generators that do this for you. But the simplest alternative would be to compile the package in multiple files without the use of `include by putting the package header is a separate file and all the other files on the compilation command line.
compile sv_lib_header.sv folder/*.sv sv_lib_footer.sv
where the header and footer files contain the package and endpackage keywords respectively.