In AXI VALID/READY Handshake we have 3 scenarios how to write Assertion

SystemVerilog
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2

In reply to SUNODH:
Your assertion with the ORing is ok.
Extracting which property has been asserted is problematic. I thought of the following solution where each of the properties calls a function with an ID upon a true. That function asserts an event based on the ID. In theory, it should work. In practice, the simulator optimizes out the evaluation of other properties on a pass of one property, thus I don’t get all the flags.
The complete model is AT http://systemverilog.us/vf/theoring.sv
The best solution for simulation is to assert the individual properties and add action blocks. The failures can be ignored. Basically, those 3 assertions would be more for debug.


event e1, e2, e3; 
     function automatic void flag(int a);
         case (a)
             0: -> e1; 
             1: -> e2; 
             2: -> e3; 
         endcase
     endfunction
  
    property p_a;  
      @(posedge clk)   a |-> (b, flag(0));
     endproperty 

     property p_b;  
      @(posedge clk)   b |-> (a, flag(1));
     endproperty 

     property p_c;  
      @(posedge clk)   a |=> (b, flag(2));
     endproperty 
     ap_all: assert property(p_a or p_b or p_c);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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