Implementing a memory model

[cooltoad]

Hello,

This is a pretty generic question.I am trying to create a reference memory model in my test environment. The model is expected to be updated as follows.Every time I see a “write” event to the memory, a monitor captures that as a packet and sends it to the scoreboard. The scoreboard then processes it and updates the appropriate memory location. The problem is, this model will be generic and is expected to be used by multiple checkers in the design. My current intended hierarchy is as follows,

 top
 |______ monitor
 |______ memory model
 |______ scoreboard
 |______ checker

I want the scoreboard to be able to update the model and the checkers to be able to read from it.
The updates can be done using analysis port, export. Can some one tell me which SV construct can be used to “access” the memory model?

[ben2]

In reply to cooltoad:

Can some one tell me which SV construct can be used to “access” the memory model?

You can put the memory model into an interface that is accessible by all models that need access to it.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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[cooltoad]

That is a very interesting approach.
Do you mean connect your environment to the memory model via an interface?
Could you elaborate a bit more on that?

[ben2]

In reply to cooltoad:

That is a very interesting approach.
Do you mean connect your environment to the memory model via an interface?
Could you elaborate a bit more on that?

Take a look at my paper at
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

Notice the static variables in class C.
You can put the memory there, as an option. That memory can be accessed by any entity that declared it. That is one option.
In that paper, I used an interface where an assertion modified a variable within the static class.
Another option is to declare the variables (e.g., memory) in the interface and have it connected it to the various class instances.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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