Implement transaction logic in driver or sequence class

UVM
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In reply to dave_59:

In reply to ak_verifsj:
Look at the last example of my DVCon paper: SystemVerilog Constraints: Appreciating What You Forgot in School to Get Better Results. You can change the constraint for HEADS to a 0 data value, or whatever represents a non-driving transaction.

Thanks that was a good suggestions. I did not think of weighted dist application here. I tried to code it but one count mismatch, I randomize 25 times and see valid==1 14 times only

bit valid;
constraint c1{valid dist {1:= 15, 0:=10};}

Is this the correct way to use dist function to get valid==1 15 times for every valid==0 10times?