UVM - Stop Hitting Your Brother Coding GuidelinesAuthors: Abstract: UVM promised a perfect world where a common set of guidelines for testbenches and connected verification IP would make a compatible, simpler world. Just don’t look too closely at the standard. UVM carries baggage from previous standards such as OVM, VMM, eRM, AVM, and more. |
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This paper describes situations where UVM provides multiple ways to solve a problem, and approaches outside of UVM, explains the issues with certain approaches, and recommends solutions, and describes the tradeoffs. View DVCon Paper. |
Authors:
Jacob Wiltgen, Ping Yeung, Jin Hou and Vinayak Desai - Mentor, A Siemens Business
Abstract:
As functional safety becomes increasingly important in today's industrial and automotive designs, many legacy de-signs have to be “upgraded” to meet the safety goal of the system. An efficient approach is to use safety synthesis and formal verification to incorporate a safety architecture into the design. The flow can consist of these major steps: 1) explore areas of the design where better fault detections are required, 2) introduce the right safety mechanisms into the design with safety synthesis, 3) validate the design changes with formal verification, and 4) perform formal fault injection to measure the diagnostic coverage.
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Author:
Rich Edelman - Mentor, A Siemens Business
Abstract:
In the hardware verification world a common and popular technique for "checking" is to use coverage. Yet, as common and popular as it is, it is still the realm of the specialist or the Verification IP. This paper will explore and simplify coverage through examples and use models. It will explore functional coverage, line coverage, expression coverage among others. It will explore coverage debug and coverage distribution.
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Author:
Matthew Ballance - Mentor, A Siemens Business
Abstract:
The Accellera PSS language standard enables users to capture a model of test intent that is portable across verification levels and execution platforms. Challenges in reusing the integration between the PSS model and the environment severely impacts the overall reuse benefits of applying PSS. This paper highlights the challenges in productively integrating PSS with the environment, and covers key criteria for a PSS/environment integration that maximizes reuse of both the environment elements and the PSS description. It describes key elements of a framework that maximizes PSS and test realization reuse across UVM-based testbench environments, and between UVM and embedded-software environments.
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Authors:
Ashish Amonkar, Kurt Takara and Avinash Agrawal - Mentor, A Siemens Business
Abstract:
Although dynamic power usage has been a concern for decades, leakage power is a big concern for today’s SoC designs below 65nm. Reducing power consumption is essential to both mobile and data center applications, where lower power contributes to either longer battery life in IoT and handheld products while minimally impacting performance. The solution has been to partition designs into multiple power domains which allows selectively reducing voltage levels or powering off partitions. Traditional low power verification only validates the functional correctness of power control logic, but it does not validate the impact of power logic on multi-clock logic.
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Authors:
Madhusudhana Reddy Lebaka, Abraham Guizer and Progyna Khondkar - Mentor, A Siemens Business
Abstract:
Integration of soft & hard macros with low power designs and conduct power aware (PA) verification are always complex and cumbersome. Specifically, in bottom up integration perspective, the extents of power domain boundary, terminal boundary, ancestor-descendant relations, power intent confinement, driver-receiver supply contexts, power states expectations, simulation state behavior, corruption semantics etc. for these macros were not well defined until UPF 3.1 (IEEE 1801-2019). As a consequence, low power macro verification solutions were not always intuitive, portable or standard. This paper distinctively studies the inherent integration features of soft & hard macros that are inevitable for low power designs today. This has been done by thoroughly identifying the semantic gaps between physical interpretations of macros with their low power orientations. With real design examples, we provided simple and manageable macro verification solutions that are portable, comply with UPF 3.1 standards and reusable in consecutive projects. This will also address verification challenges between flat frontend simulation flows to the hierarchical backend flows. Our motivation is to create a complete low power integration and verification solution for soft & hard macros that will benefit the design, verification, integration, implementation, as well IP vendor industries.
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Authors:
Soumya Palit, Anwesha Choudhury, and Kurt Takara - Mentor, A Siemens Business
Abstract:
With increasing complexity of modern SoCs, the reset architecture is becoming more and more complex and hence Reset Domain Crossing (RDC) verification has become a critical step in the verification cycle. As the design size continues to increase, flat RDC verification on full SoC becomes infeasible. Additionally, as different modules of a SoC are developed by different designers in different geographies, there is need for a distributed RDC verification mechanism, where each module can be verified separately and then integrated for complete RDC verification on the SoC. The primary
challenge of distributed RDC verification methodology is that the methodology should be able to understand the reset architecture of the complete SoC even if the verification happens independently for each IP. In this paper, we present a RDC verification approach that supports IP-based designs, which is seamless to use and does not compromise on accuracy or debug. The proposed approach will be based on a generic data model, that can capture RDC intent of any block or subsystem and the model can be seamlessly used across releases, across designs wherever the IP is reused.
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Author:
Dave Rich - Mentor, A Siemens Business
Abstract:
Constrained Random Verification (CRV) addresses the time-consuming task of writing individual directed tests for complex systems. We sometimes say that CRV automates writing tests for quickly producing the test cases you can think of, or hitting the corner cases you didn’t. But the reality is, like with any computer programming language, your code executes exactly the way it is written, and has no concern for what you were thinking. In particular when coding constraints, this manifests as results that satisfy the constraints, but may not match what you intend. Crashes or conflicting constraint failures are usually easier to resolve because of their abrupt termination. However, without an abrupt termination, you may not notice anything wrong with the results until much later in the process; perhaps after you check your functional coverage reports. This paper looks at two of the most common issues when constraint solver results do not match your intent: 1) not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra, and 2) not understanding the affect probability has on choosing solution values. These are subjects you may have learned (or slept through) in school long ago and need refreshing. This paper presents a background defining how SystemVerilog constraints work, and how these issues play into getting unwanted results. Also, it offers a few coding recommendations for improving your code to get better results along the way.
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Author:
Madhur Bhargava - Mentor, A Siemens Business
Abstract:
The increasing complexity and growing demand for energy efficient electronic systems has resulted in sophisticated power management architectures. To keep up with the pace, the IEEE 1801 standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs. With the recent release of the IEEE 1801-2018 (UPF 3.1), several new features have been added along with improving clarity on existing features. With this, we have five UPF standards posing some questions about the compatibility, differences, and challenges related to migration and its impact on verification. For any low-power designer the big question arises which is the right standard for my design. In this paper, firstly we will provide an in-depth analysis and relevant examples of all the new features introduced by the UPF 3.1 along with highlighting any semantics differences with the earlier versions. The paper will include detailed analysis of broader topics which have been semantically changed over the UPF versions.
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Authors:
Akanksha Gupta, Anwesha Choudhury and Kurt Takara - Mentor, A Siemens Business
Abstract:
Today, in automotive circuits, as electronic systems are increasingly replacing mechanical systems, the concerns to make system fail-safe have increased. However, as with all electronics, things can go wrong sometimes, hardware can fail. Modern automotive Systems on Chips (SoCs) typically contain multiple asynchronous reset signals to ensure systematic functional recovery from such unexpected situations and faults. The complex reset architecture leads to a new set of problems such as reset domain crossings (RDCs). The conventional clock domain verification methodologies cannot identify such critical bugs. In this paper, we present a systematic methodology to identify critical reset domain bugs and solve them to ensure a high degree of quality as required in automotive SoCs.
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