How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros
Authors:
Madhusudhana Reddy Lebaka, Abraham Guizer and Progyna Khondkar - Mentor, A Siemens Business
Abstract:
Integration of soft & hard macros with low power designs and conduct power aware (PA) verification are always complex and cumbersome. Specifically, in bottom up integration perspective, the extents of power domain boundary, terminal boundary, ancestor-descendant relations, power intent confinement, driver-receiver supply contexts, power states expectations, simulation state behavior, corruption semantics etc. for these macros were not well defined until UPF 3.1 (IEEE 1801-2019). As a consequence, low power macro verification solutions were not always intuitive, portable or standard. This paper distinctively studies the inherent integration features of soft & hard macros that are inevitable for low power designs today. This has been done by thoroughly identifying the semantic gaps between physical interpretations of macros with their low power orientations. With real design examples, we provided simple and manageable macro verification solutions that are portable, comply with UPF 3.1 standards and reusable in consecutive projects. This will also address verification challenges between flat frontend simulation flows to the hierarchical backend flows. Our motivation is to create a complete low power integration and verification solution for soft & hard macros that will benefit the design, verification, integration, implementation, as well IP vendor industries.
View DVCon Paper.
