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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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  • Featured Presentations from DVCon US 2020

Featured Presentations from DVCon US 2020

Mentor®, a Siemens Business, has pioneered technology to close the design and verification gap to improve productivity and quality of results. Catapult® High-Level Synthesis for C-level verification and PowerPro® for power analysis; Questa® for simulation, low-power, VIP, CDC, Formal and support for UVM and Portable Stimulus; Veloce® for hardware emulation and system of systems verification, unified with the Visualizer™ debug environment.

The following papers, posters and recordings were featured at DVCon US 2020.

   DVCON US 2020

Featured Invited Talk:

Featured Short Workshop:

FPGA Verification Maturity: A Quantitative Analysis

FPGA Verification Maturity: A Quantitative Analysis

Released on March 26th, 2020

Author:
Harry Foster - Mentor, A Siemens Business

Overview:
While multiple studies on IC/ASIC functional verification trends have been published, there have been no studies specifically focused on FPGA verification trends. To address this dearth of information, Harry presents the results from a recent large industry study on functional verification. The findings from this study provide invaluable insight into the state of today’s FPGA market in terms of both design and verification trends. What is unique about this study is that for the first time the impact of this growing complexity has been quantified in terms verification effectiveness and effort.

View Recording | Slides

Closing and Creating Gaps Between Design and Verification

Mind the Gap(s): Closing and Creating Gaps Between Design and Verification

Released on March 31st, 2020

Authors:
Chris Giles & Kurt Takara - Mentor, A Siemens Business

Overview:
Verification takes many forms. What’s common to all development projects is that they must deal with the gaps. Learn how to identify gaps, create gaps to help your development process align with your immutable gaps, and then how to close the remaining uncovered gaps with precision such as gaps between design and implementation, as well as organizational or time-based gaps.

View Recording | Slides

Best Paper & Poster - 2nd Place:

UVM - Stop Hitting Your Brother Coding Guidelines

UVM - Stop Hitting Your Brother Coding Guidelines

Authors:
Rich Edelman and Chris Spear - Mentor, A Siemens Business

Abstract:
This paper show multiple ways to write UVM code, and explains the tradeoffs.

UVM promised a perfect world where a common set of guidelines for testbenches and connected verification IP would make a compatible, simpler world. Just don’t look too closely at the standard. UVM carries baggage from previous standards such as OVM, VMM, eRM, AVM, and more.

   DVCon 2020 Best Paper - 2nd Place

This paper describes situations where UVM provides multiple ways to solve a problem, and approaches outside of UVM, explains the issues with certain approaches, and recommends solutions, and describes the tradeoffs.

View DVCon Paper.

Deadlock Verification For Dummies – The Easy Way Using SVA and Formal

Deadlock Verification For Dummies – The Easy Way Using SVA and Formal

Authors:
Mark Eslinger, Jeremy Levitt and Joe Hupcey III - Mentor, A Siemens Business

Abstract:
RTL simulation cannot directly tell if a digital system is deadlocked — you can only observe that nothing has happened for a long time (so when should you get worried that nothing is happening?), and you cannot can’t differentiate between situations where your system is truly locked up from a situation where the right stimulus hasn’t come along to take the design out of a local minimum.

   DVCon 2020 Best Poster - 2nd Place

In this paper we will show how combining the above concepts using normal SVA liveness properties allows for RTL engineers to achieve the benefit of formal deadlock analysis without the iterative component or learning a non-standard assertion language. Deadlock verification for dummies!

View Recording | Paper | Poster.

Featured Papers:

Are You Safe Yet? Safety Mechanism Insertion and Validation

Are You Safe Yet? Safety Mechanism Insertion and Validation

Authors:
Jacob Wiltgen, Ping Yeung, Jin Hou and Vinayak Desai - Mentor, A Siemens Business

Abstract:
As functional safety becomes increasingly important in today's industrial and automotive designs, many legacy de-signs have to be “upgraded” to meet the safety goal of the system. An efficient approach is to use safety synthesis and formal verification to incorporate a safety architecture into the design. The flow can consist of these major steps: 1) explore areas of the design where better fault detections are required, 2) introduce the right safety mechanisms into the design with safety synthesis, 3) validate the design changes with formal verification, and 4) perform formal fault injection to measure the diagnostic coverage.

View DVCon Paper.

COVERGATE: Coverage Exposed

COVERGATE: Coverage Exposed

Author:
Rich Edelman - Mentor, A Siemens Business

Abstract:
In the hardware verification world a common and popular technique for "checking" is to use coverage. Yet, as common and popular as it is, it is still the realm of the specialist or the Verification IP. This paper will explore and simplify coverage through examples and use models. It will explore functional coverage, line coverage, expression coverage among others. It will explore coverage debug and coverage distribution.

View DVCon Paper.

Designing PSS Environment Integration for Maximum Reuse

Designing PSS Environment Integration for Maximum Reuse

Author:
Matthew Ballance - Mentor, A Siemens Business

Abstract:
The Accellera PSS language standard enables users to capture a model of test intent that is portable across verification levels and execution platforms. Challenges in reusing the integration between the PSS model and the environment severely impacts the overall reuse benefits of applying PSS. This paper highlights the challenges in productively integrating PSS with the environment, and covers key criteria for a PSS/environment integration that maximizes reuse of both the environment elements and the PSS description. It describes key elements of a framework that maximizes PSS and test realization reuse across UVM-based testbench environments, and between UVM and embedded-software environments.

View DVCon Paper.

Did Power Management Break My CDC Logic?

Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock-Domain Crossing Verification

Authors:
Ashish Amonkar, Kurt Takara and Avinash Agrawal - Mentor, A Siemens Business

Abstract:
Although dynamic power usage has been a concern for decades, leakage power is a big concern for today’s SoC designs below 65nm. Reducing power consumption is essential to both mobile and data center applications, where lower power contributes to either longer battery life in IoT and handheld products while minimally impacting performance. The solution has been to partition designs into multiple power domains which allows selectively reducing voltage levels or powering off partitions. Traditional low power verification only validates the functional correctness of power control logic, but it does not validate the impact of power logic on multi-clock logic.

View DVCon Paper.

How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros

How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros

Authors:
Madhusudhana Reddy Lebaka, Abraham Guizer and Progyna Khondkar - Mentor, A Siemens Business

Abstract:
Integration of soft & hard macros with low power designs and conduct power aware (PA) verification are always complex and cumbersome. Specifically, in bottom up integration perspective, the extents of power domain boundary, terminal boundary, ancestor-descendant relations, power intent confinement, driver-receiver supply contexts, power states expectations, simulation state behavior, corruption semantics etc. for these macros were not well defined until UPF 3.1 (IEEE 1801-2019). As a consequence, low power macro verification solutions were not always intuitive, portable or standard. This paper distinctively studies the inherent integration features of soft & hard macros that are inevitable for low power designs today. This has been done by thoroughly identifying the semantic gaps between physical interpretations of macros with their low power orientations. With real design examples, we provided simple and manageable macro verification solutions that are portable, comply with UPF 3.1 standards and reusable in consecutive projects. This will also address verification challenges between flat frontend simulation flows to the hierarchical backend flows. Our motivation is to create a complete low power integration and verification solution for soft & hard macros that will benefit the design, verification, integration, implementation, as well IP vendor industries.

View DVCon Paper.

Scalable Reset Domain Crossing Verification Using Hierarchical Data Model

Scalable Reset Domain Crossing Verification Using Hierarchical Data Model

Authors:
Soumya Palit, Anwesha Choudhury, and Kurt Takara - Mentor, A Siemens Business

Abstract:
With increasing complexity of modern SoCs, the reset architecture is becoming more and more complex and hence Reset Domain Crossing (RDC) verification has become a critical step in the verification cycle. As the design size continues to increase, flat RDC verification on full SoC becomes infeasible. Additionally, as different modules of a SoC are developed by different designers in different geographies, there is need for a distributed RDC verification mechanism, where each module can be verified separately and then integrated for complete RDC verification on the SoC. The primary
challenge of distributed RDC verification methodology is that the methodology should be able to understand the reset architecture of the complete SoC even if the verification happens independently for each IP. In this paper, we present a RDC verification approach that supports IP-based designs, which is seamless to use and does not compromise on accuracy or debug. The proposed approach will be based on a generic data model, that can capture RDC intent of any block or subsystem and the model can be seamlessly used across releases, across designs wherever the IP is reused.

View DVCon Paper.

SystemVerilog Constraints: Get Better Results

SystemVerilog Constraints: Appreciating What You Forgot in School to Get Better Results

Author:
Dave Rich - Mentor, A Siemens Business

Abstract:
Constrained Random Verification (CRV) addresses the time-consuming task of writing individual directed tests for complex systems. We sometimes say that CRV automates writing tests for quickly producing the test cases you can think of, or hitting the corner cases you didn’t. But the reality is, like with any computer programming language, your code executes exactly the way it is written, and has no concern for what you were thinking. In particular when coding constraints, this manifests as results that satisfy the constraints, but may not match what you intend. Crashes or conflicting constraint failures are usually easier to resolve because of their abrupt termination. However, without an abrupt termination, you may not notice anything wrong with the results until much later in the process; perhaps after you check your functional coverage reports. This paper looks at two of the most common issues when constraint solver results do not match your intent: 1) not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra, and 2) not understanding the affect probability has on choosing solution values. These are subjects you may have learned (or slept through) in school long ago and need refreshing. This paper presents a background defining how SystemVerilog constraints work, and how these issues play into getting unwanted results. Also, it offers a few coding recommendations for improving your code to get better results along the way.

View DVCon Paper.

UPF 1.0, 2.0, 3.0 and Now 3.1: Which is the Right Standard for My Design?

UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and now UPF 3.1: The big Q Which is the Right Standard for My Design?

Author:
Madhur Bhargava - Mentor, A Siemens Business

Abstract:
The increasing complexity and growing demand for energy efficient electronic systems has resulted in sophisticated power management architectures. To keep up with the pace, the IEEE 1801 standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs. With the recent release of the IEEE 1801-2018 (UPF 3.1), several new features have been added along with improving clarity on existing features. With this, we have five UPF standards posing some questions about the compatibility, differences, and challenges related to migration and its impact on verification. For any low-power designer the big question arises which is the right standard for my design. In this paper, firstly we will provide an in-depth analysis and relevant examples of all the new features introduced by the UPF 3.1 along with highlighting any semantics differences with the earlier versions. The paper will include detailed analysis of broader topics which have been semantically changed over the UPF versions.

View DVCon Paper.

Systematic Methodology to Solve Reset Challenges in Automotive SoCs

Systematic Methodology to Solve Reset Challenges in Automotive SoCs

Authors:
Akanksha Gupta, Anwesha Choudhury and Kurt Takara - Mentor, A Siemens Business

Abstract:
Today, in automotive circuits, as electronic systems are increasingly replacing mechanical systems, the concerns to make system fail-safe have increased. However, as with all electronics, things can go wrong sometimes, hardware can fail. Modern automotive Systems on Chips (SoCs) typically contain multiple asynchronous reset signals to ensure systematic functional recovery from such unexpected situations and faults. The complex reset architecture leads to a new set of problems such as reset domain crossings (RDCs). The conventional clock domain verification methodologies cannot identify such critical bugs. In this paper, we present a systematic methodology to identify critical reset domain bugs and solve them to ensure a high degree of quality as required in automotive SoCs.

View DVCon Paper.

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