In reply to hrishikeshadn:
The answer to your question is highly opinionated. It may come down to where you have experience or resources available to help you through the process.
In general, certain kinds of applications will favor certain languages (and remember SystemC is not a language; it is a library on top of the C++ language). It might be easier to express the description of an application in one language as well as getting better performance.
SystemC is certainly favorable for large data-centric, algorithmic, and untimed models; whereas SystemVerilog is better suited for bit-level, event-driven, multiple clock or asynchronous models.