Hi,
I have a basic question. It seems to me that “illegal bins” in the coverage and an assertion are trying to check “whether a forbidden thing is happening ?”. Why two ways of achieving the same thing. When to use what ? Can anyone give some examples / use cases ?
Regards,
Madhu
SystemVerilog is a very feature laden language that has brought in functionality from numerous other languages. This does create overlapping features sometimes.
My advice is to stick with assertions for checking the design, and only use illegal_bins as a debugging aid for checking problems with your testbench. The reason is that assertions give you much better options for providing better error messages through the use of an action block, and you have much more control over the execution of an assertion with way of changing the severity individually.
In reply to dave_59:
Thanks Dave. I understood the part to when to use what ?
However, I am not very clear the part below.
you have much more control over the execution of an assertion with way of changing the severity individually.
Can you please explain, how can we control the severity for an assertion (possibly with an example) ?
Thanks,
Madhu
In reply to mseyunni:
assert property (...) else $error(...); // run time error - simulation continues
assert property (...) else $fatal(..); // simulation halts immediately
assert property (...) else `uvm_error("ID",...) // run time error - UVM gives you the ability to suppress, change the severity, callbacks, and much more.