SystemVerilog is a very feature laden language that has brought in functionality from numerous other languages. This does create overlapping features sometimes.
My advice is to stick with assertions for checking the design, and only use illegal_bins as a debugging aid for checking problems with your testbench. The reason is that assertions give you much better options for providing better error messages through the use of an action block, and you have much more control over the execution of an assertion with way of changing the severity individually.