Ignoring Cross Coverage Automatic bins

SystemVerilog
1

Hi,
I’d like to specify the exact bins I want to hit in cross coverage and then ignore any automatically created bins. Is there any way to stop the creation of automatic bins?

I know I could use ignore_bins but sometimes it’s quite difficult to come up with an expression that ignores the automatically created bins. A simple example is the following:

cmd : coverpoint trans.cmd
{
  bins cmd1 = {1};
  bins cmd2 = {2};
  bins cmd3 = {3};
}

source : coverpoint trans.source
{
  bins master1 = {1};
  bins master2 = {2};
  bins master3 = {3};
}

dest : coverpoint trans.dest
{
  bins slave1 = {1};
  bins slave2 = {2};
  bins slave3 = {3};
}


MyCmds : cross cmd, source, dest
{
  bins cmd1 = binsof(cmd.cmd1) && binsof(source.master1) && binsof(dest.slave1);
  bins cmd2 = binsof(cmd.cmd2) && binsof(source.master2) && binsof(dest.slave2);
  bins cmd3 = binsof(cmd.cmd3) && binsof(source.master3) && binsof(dest.slave3);
}
2

In this particular case, three additional coverpoints would be better than trying to create the proper bins of a cross.

c1 : coverpoint  trans.cmd == 1 && trans.source == 1 && trans.dest == 1
{ bins hit = {1}; }
c2 : coverpoint  trans.cmd == 2 && trans.source == 2 && trans.dest == 2
{ bins hit = {1}; }
c3 : coverpoint  trans.cmd == 3 && trans.source == 3 && trans.dest == 3
{ bins hit = {1}; }
3

In reply to dave_59:

Hi. Dave :
It seems the DEFAULT is not supported in CROSS, Not sure why?

4

In reply to aming:

The current behavior of a cross is that there is always a auto-generated set of default bins.

5

In reply to dave_59:

Thanks Dave, that worked perfectly.
I looked through a lot of coverage examples and never spotted one which had an expression as the coverpoint so I didn’t know it was possible to do that. Most examples had expressions as part of the bins.