Ignoring Cross Coverage Automatic bins

SystemVerilog
2

In this particular case, three additional coverpoints would be better than trying to create the proper bins of a cross.

c1 : coverpoint  trans.cmd == 1 && trans.source == 1 && trans.dest == 1
{ bins hit = {1}; }
c2 : coverpoint  trans.cmd == 2 && trans.source == 2 && trans.dest == 2
{ bins hit = {1}; }
c3 : coverpoint  trans.cmd == 3 && trans.source == 3 && trans.dest == 3
{ bins hit = {1}; }