If the default argument is initialized in the base_class function there is no error. But for the following explicit super.new the following error is obtained. Thanks in Advance

SystemVerilog
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3

Hi Sir,
In the code if the base class is declared with the value 6 there is no error,but when I try to assign value using super.new(6) then the error is seen.
Is it because of the base’s new is always called, but the “data” argument is NOT provided for the IMPLICIT call to new in base_class.
Even then 1)Add default argument in constructor of base class.
—function new(bit[15:0] data=6)—
2)Explicitly call super.new with required arguments.
------super.new(6);-----
Both should have worked but I see only first option is working for the above code.So should I follow only first option??