I have connected VHDL DUT to SVerilog testbench and used ModelSim for verifying the DUT.can i use modelsim?did i connect DUT properly?please suggest me

SystemVerilog
1
  • Compiling interface intf

** Error: C:/Modeltech_pe_edu_10.3b/examples/prtr1/Classifier_Codes/trialsv.sv(8): (vlog-13006) Could not find the package (top1). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

my code is

entity top1 is
generic(word_length:integer :=32);

port(
clk,reset,ready : in std_logic;
data_in: in std_logic_vector(word_length -1 downto 0);
h: out std_logic_vector(word_length/4 -1 downto 0)
);
end top1;

interface intf #(word_length=32) (input clk);
logic reset, ready;
logic [word_length -1:0] in;
logic [word_length/4 -1:0] h;
endinterface

import top1::*;

module top1(input clk, input reset, input ready, input in, output h);
endmodule

module test (itf ip);
endmodule

module testbench();
logic clk;
itf ii(clk);
top1 inst_dut(ii.clk, ii.reset, ii.ready, ii.in, ii.h);
test inst(ii);
endmodule

2

You don’t need


import top1::*;

module top1(input clk, input reset, input ready, input in, output h);
endmodule

That import line is attempting to load an SV package called “top1” which doesn’t exist, that is the error message you are getting. You don’t need to ‘import’ or otherwise do anything special to allow VHDL to be instantiated in Verilog

Also, you don’t want to have both a module in the SV named ‘top1’ and your vhdl entity named ‘top1’ They will overwrite each other and your simulation will only have which ever one was compiled last.

Finally your example has a number of typos, on things like the interface name not being consistent ‘itf’ vs ‘intf’

3

In reply to prtr:

This time i want to be clear
i am having VHDL entity named top1 and saved with top1.vhd in the library named prtr1
now i to verify using system verilog module named testbench and saved it as svtrial.sv in the library prtr1
the code in the svtrial.sv goes down here

interface intf #(word_length=32) (input bit clk);
logic reset, ready;
logic [word_length -1:0] in;
logic [word_length/4 -1:0] h;
endinterface

module test (intf ip);
initial
begin
repeat(5)
begin
ip.reset=1;
#100 ip.reset=0;ip.load=1;ip.in=$urandom();
#100000 ;
end
end
endmodule

module testbench();
bit clk;
intf #(32) ii(clk);
top1 inst_dut(.clk(ii.clk), .reset(ii.reset), .ready(ii.ready), .in(ii.in), .h(ii.h));
test inst(ii);

initial
forever #(50) clk=~clk;

endmodule

when iam simulating the above code i am getting the follwing error

** Fatal: (vsim-3039) C:/Modeltech_pe_edu_10.3b/examples/prtr1/Classifier_Codes/trialsv.sv(25): Instantiation of ‘top1’ failed.

Time: 0 ns Iteration: 0 Instance: /testbench File: C:/Modeltech_pe_edu_10.3b/examples/prtr1/Classifier_Codes/trialsv.sv

FATAL ERROR while loading design

now my question is this correct way connecting VHDL dut to sverilog testbench?
please help me to implement the program