I have connected VHDL DUT to SVerilog testbench and used ModelSim for verifying the DUT.can i use modelsim?did i connect DUT properly?please suggest me

SystemVerilog
2

You don’t need


import top1::*;

module top1(input clk, input reset, input ready, input in, output h);
endmodule

That import line is attempting to load an SV package called “top1” which doesn’t exist, that is the error message you are getting. You don’t need to ‘import’ or otherwise do anything special to allow VHDL to be instantiated in Verilog

Also, you don’t want to have both a module in the SV named ‘top1’ and your vhdl entity named ‘top1’ They will overwrite each other and your simulation will only have which ever one was compiled last.

Finally your example has a number of typos, on things like the interface name not being consistent ‘itf’ vs ‘intf’